1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor memory device that may efficiently map an internal address internally used in the memory cell array of the semiconductor memory device in response to an external address that is applied from the outside of the semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices are generally divided into volatile semiconductor memory devices and non-volatile semiconductor memory devices. Recently, there are increasing demands for the non-volatile memory devices that are capable of performing program and erase operations without a refresh operation, which is an operation of reprogramming a data at a predetermined cycle.
FIG. 1 illustrates a structure of a memory cell array in a non-volatile memory device according to a prior art where pages are divided into even pages and odd pages and into main pages and spare pages according to column addresses.
Referring to FIG. 1, the memory cell array of the conventional non-volatile memory device includes even pages and odd pages that are decided according to a column address, and each page is divided into a main memory array page and a spare memory array page.
In other words, the memory cell array of the conventional non-volatile memory device includes a main even page MAIN_EVEN (1), a main odd page MAIN_ODD (2), a spare even page SPARE_EVEN (3), and a spare odd page SPARE_ODD (4) that are sequentially disposed according to column addresses.
FIG. 1 illustrates an example of such memory cell array. The entire size of the exemplary memory cell array in a column direction is 18K and the main pages occupy 16K out of the entire size while the spare pages occupy 2K.
According to the prior art, the Initial column addresses of the main even page MAIN_EVEN (1), the main odd page MAIN_ODD (2), the spare even page SPARE_EVEN (3), and the spare odd page SPARE_ODD (4) are ‘0 0000 00 0000 0000’, ‘0 1000 00 0000 0000’, ‘1 0000 00 0000 0000’, and ‘1 0001 00 0000 0000’, respectively.
In short, the pages of the memory cell array are sequentially disposed in the order of the main even page MAIN_EVEN (1), the main odd page MAIN_ODD (2), the spare even page SPARE_EVEN (3), and the spare odd page SPARE_ODD (4). According to the structure of the prior art, it is possible to perform common column address decoding operation with differentiation of the main even page MAIN_EVEN (1) and the main odd page MAIN_ODD (2) by the upper second bit (‘0’ or ‘1’) and with differentiation of the spare even page SPARE_EVEN (3) and the spare odd page SPARE_ODD (4) by the upper fifth bit (‘0’ or ‘1’).
Meanwhile, high-speed interface of a non-volatile memory device is becoming more significant. For the high-speed interface, it is essential to realize a ‘half page read operation’ to reduce a read time tR during an All Bit Line (ABL) read operation. During the half page read operation, the main even page MAIN_EVEN (1) and the spare even page SPARE_EVEN (3) should be sequentially read or the main odd page MAIN_ODD (2) and the spare odd page SPARE_ODD (4) should be sequentially read.
However, according to the structure of the prior art shown in FIG. 1, where the pages of the memory cell array are sequentially disposed in the order of the main even page MAIN_EVEN (1), the main odd page MAIN_ODD (2), the spare even page SPARE_EVEN (3), and the spare odd page SPARE_ODD (4), it is hard to perform the ‘half page read operation’ in a burst mode. When data are inputted/outputted in the burst mode, that is, when data are inputted/outputted through sequential change of column addresses, the spare even page SPARE_EVEN (3) cannot be accessed right after access of the main even page MAIN_EVEN (1) because of disposition of the main odd page MAIN_ODD (2) between the main even page MAIN_EVEN (1) and the spare even page SPARE_EVEN (3). In other words, it is hard to realize the half page read operation according to the structure of the prior art shown in FIG. 1 in the burst mode. Herein, the burst mode means a mode in which an operation of sequential data input/output is performed with reception of an initial column address from the outside of the semiconductor memory device, internal counting of an address value sequentially starting from the received initial column address, and access of the memory cell of internally counted addresses, which are sequential.
In order to realize the half page read operation with the structure of the prior art shown in FIG. 1, when accessing the spare even page SPARE_EVEN (3) or the spare odd page SPARE_ODD (4), the semiconductor memory device has to get out of the burst mode and then receive a column address for the page from the outside of the semiconductor device, which means turning to an operation of random data input/output and causing an increase in time for the half page read operation. Thus, great deterioration of the overall performance of the non-volatile semiconductor memory device may occur.
FIG. 2 illustrates a structure of another conventional memory cell array in a non-volatile memory device where pages are divided into even pages and odd pages and into main pages and spare pages according to column addresses. The structure of a memory cell array shown in FIG. 2 is suggested to alleviate the concern present in the conventional non-volatile memory device shown in FIG. 1.
Referring to FIG. 2, just as illustrated in FIG. 1, the memory cell array includes even pages and odd pages according to column addresses, and each page is divided into a main memory array page and a spare memory array page.
The pages of the memory cell array shown in FIG. 2 are sequentially disposed in the order of a main even page MAIN_EVEN (1), a spare even page SPARE_EVEN (2), a main odd page MAIN_ODD (3), and a spare odd page SPARE_ODD (4).
In other words, the non-volatile memory device illustrated in FIG. 2 defines the page sequence according to column addresses in the memory cell array to realize the half page read operation in the burst mode. Therefore, the non-volatile memory device illustrated in FIG. 2 is capable of sequentially accessing the spare even page SPARE_EVEN (2) right after access of the main even page MAIN_EVEN (1), and capable of sequentially accessing the spare odd page SPARE_ODD (4) right after access of the main odd page MAIN_ODD (3) for the half page read operation in the burst mode.
According to the prior art shown in FIG. 2, however, the column address scheme becomes different as well, and it is impossible to perform the common column address decoding operation of the prior art shown in FIG. 1. For the convenience of explanation, it is assumed that the size of the memory cell array shown in FIG. 2 is same as FIG. 1.
According to the prior art shown in FIG. 2, the initial column addresses of the main even page MAIN_EVEN (1), the spare even page SPARE_EVEN (2), the main odd page MAIN_ODD (3), and the spare odd page SPARE_ODD (4) are ‘0 0000 00 0000 0000’, ‘0 1000 00 0000 0000’, ‘0 1001 00 0000 0000’, and ‘1 0001 00 0000 0000’, respectively. Compared with the structure shown in FIG. 1, the sequence of the spare even page SPARE_EVEN (2) and the main odd page MAIN_ODD (3) are switched with each other.
As described above, according to the structure of the prior art shown in FIG. 1, the pages of the memory cell array are sequentially disposed in the order of the main even page MAIN_EVEN (1), the main odd page MAIN_ODD (2), the spare even page SPARE_EVEN (3), and the spare odd page SPARE_ODD (4), and thus it is possible to perform common column address decoding operation with differentiation of the main even page MAIN_EVEN (1) and the main odd page MAIN_ODD (2) by the upper second bit (‘0’ or ‘1’) and with differentiation of the spare even page SPARE_EVEN (3) and the spare odd page SPARE_ODD (4) by the upper fifth bit (‘0’ or ‘1’). However, according to the structure shown in FIG. 2, the main even page MAIN_EVEN (1) and the main odd page MAIN_ODD (3) are different not only in the upper second bit but also in the upper fifth bit. They are not distinguished by the upper second bit, which means that it is impossible to perform the common column address decoding operation of the prior art shown in FIG. 1. This is because not only the value of the upper second bit but also the value of the upper fifth bit is different. The same concern is present in the spare even page SPARE_EVEN (2) and the spare odd page SPARE_ODD (4). Because of the impossibility of the common column address decoding operation, the column decoding operation has to be performed separately for the even page and for the odd page, which causes needs for independent elements that respectively decode the even page and the odd page, and thus creating the need for double sized column decoding unit. The doubled size of the column decoder also means that the number of CAM (Content Addressable Memory) latches for storing repair information has to be doubled and the number of decoding lines passing through a page buffer has to be increased. This increases the chip size.
Therefore, the prior art shown in FIG. 2 may not be a solution to the half page read operation in the burst mode.